1. Field of the Disclosure
The present invention relates to semiconductor devices and methods for fabricating the same, in which an extended drain region is self-aligned to a gate.
2. Discussion of the Related Art
In general, a DEMOS (Depletion-Enhancement CMOS, or drain-extended CMOS) device which can operate at a high voltage has an extended drain structure. However, in conventional DEMOS devices, the drain structure is not self-aligned to a gate, which can result in mismatch characteristic (e.g., with regard to drain current or threshold voltage) in conventional DEMOS devices, as shown in FIGS. 1A and 1B.
More specifically, the drain regions 14 and 28 in FIG. 1A or 1B are not self-aligned with the gates 13 and 30, respectively.
A CMOS device having a conventional LDD structure may have poor hot carrier injection (HCI) and mismatch characteristics due to shallow drain junctions and high density doping of the drain region near the gate and the channel region.